This article discusses in detail the background and importance of the recently established Universal Chiplet Interconnect (UCIe) Standard for use in the semiconductor industry.
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Importance of Chiplets in Semiconductor Applications
Chiplets, the latest advancement in the system on a chip (SoC) model, have garnered considerable attention in recent years for semiconductor applications. The fundamental logic for chiplets is that several recent advancements have made the industry's conventional way of designing ever-larger chips less compelling, both technically and economically.
Thus, rather than developing refined monolithic devices that integrate all crucial components on single crystal silicon die, key semiconductor companies are now developing products that separate large models into small chunks (hence the term "chiplets") and cleverly integrate them.
The rationale for this adjustment goes to the core of many of the semiconductor industry's transformative achievements. To begin, typical Moore's Law gains in transistors size reduction have slowed significantly, making it impossible (and very costly) to lower the processing layouts of all the parts within a monolithic chip design. Furthermore, it appears that several critical components of modern microchips, such as analog I/O and certain storage systems, typically deliver worse performance on smaller devices. As a result, some semiconductor elements benefit from remaining in bigger process production sizes.
Motivation for On-Package Integration of Chiplets
Numerous solutions are available for on-package chiplets. As die sizes rise to suit increasing quality standards, devices are approaching the die reticle limitation. Several examples are multi-core CPUs with tens of cores or extremely massive fanout controllers. Even when a die fits inside the reticle restriction, it may be advantageous to join numerous smaller dies in packaging for productivity maximization and die recycling across various market segments. These scale-up capabilities are enabled by the on-package interconnection of similar dies.
Another reason for on-package connectivity is to reduce the whole inventory expenditure, both at the product and project level, and to gain a competitive edge in terms of product availability. Additionally, the incorporation of chiplets on a package allows a customer to determine various trade-offs for various market segments by selecting alternative die counts and kinds.
For instance, depending on the segment's requirements, the amount of computation, storage, and I/O dies may be varied. UCIe is a forward-thinking on-package interconnect that understands these use scenarios and is ready to revolutionize the industry.
Advantages of an Industry-Wide Acceptable Standard
A thriving ecosystem requires an open industry standards organization that defines specifications with appealing key performance indicators (KPIs) which accommodate a broad variety of usages, as well as full conformity and an interoperable framework. The UCIe Specification includes industry-leading KPIs, debug assistance, and provisions for adherence. On-package die implantation has grown as a technique throughout the production, manufacturing, and testing industries.
UCIe is the product of industry experts collaborating to create a single specification that enables the smooth interoperation of many chiplets from disparate suppliers. While the advocates of UCIe span the cloud, chip production, OSAT, intellectual property providers, and chip manufacturers, the UCIe collaboration is open to everybody. UCIe is positioned to become the de facto on-package interconnect for chiplets, enabling the development of a robust open chiplet ecosystem.
Usage Models and KPIs Driven by UCIe Specification
UCIe is a multiple-layer system. The Die-to-Die adaptor manages the chiplets' connection status and parameter setting. It provides potentially reliable data delivery using a cyclic redundancy check (CRC) and link-level restart method. It describes the fundamental mediation process when several protocols are enabled.
When the converter is required for dependable transfer, a 256-byte FLIT (flow control unit) specifies the basic transfer method. UCIe 1.0 establishes two distinct forms of packing. For cost-effective functionality, the conventional package (2D) is employed. The power-efficient result is enhanced via the use of sophisticated packaging. Numerous commercially available choices exist. The UCIe standard encompasses all possible package configurations under these classes. Additionally, it allows two distinct usage types.
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The first is package-level interconnection, which enables energy- and cost-efficient performance. Components mounted on the board, such as storage, processors, network equipment, and modems, may be connected at the package level, with applications ranging from handsets to high-end workstations. The second use is to allow off-package connectivity through a variety of media types (e.g., optical, electrical cable, mmWave).
Conclusion and Future Perspective
There is an enormous need for an accessible chiplet ecosystem that will accelerate development throughout the computational spectrum. UCIe is an appealing combination of power efficiency and economic effectiveness. The premise that it is an open platform with a plug-and-play architecture, inspired by multiple successful specifications, and promoted by the appropriate collection of leading companies, ensures widespread acceptance.
The partnership is likely to promote even more energy-efficient and cost-effective opportunities in the future as bump pitches continue to drop and 3D connectivity becomes more prevalent. These may need broader networks that operate slower and are closer to on-die communication in terms of delay, bandwidth, and power management. In the coming decades, advancements in packaging and semiconductor production technologies will reshape the computing world. UCIe is ideally positioned to allow ecosystem developments to fully benefit from these technological advancements as they occur.
References and Further Reading
O’Donnell, B., 2022. The future of semiconductors is UCIe. [Online]
Available at: https://www.techspot.com/news/93694-future-semiconductors-ucie.html
[Accessed 31 March 2022].
Sharma, D. D. D., 2022. Universal Chiplet Interconnect Express (UCIe)®: Building an open chiplet ecosystem, s.l.: UCIe.
Silva, J., 2022. Arm, Intel, TSMC, AMD, Google, and more industry leaders form the Universal Chiplet Interconnect Express (UCIe) standard. [Online]
Available at: https://www.techspot.com/news/93617-universal-chiplet-interconnect-express-hopes-standardize-chiplet-architecture.html
[Accessed 31 March 2022].
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