Mar 5 2009
In an effort to develop new semiconductor packaging technologies, DuPont Wafer Level Packaging Solutions, part of DuPont Electronic Technologies, has signed a joint-development agreement with Nippon Kayaku Co. Ltd. (NKC) and its wholly owned subsidiary, MicroChem Corp. Wafer level packaging refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing.
DuPont conducts research at its Semiconductor Materials Technical Center in Taiwan.
The electronic materials developed under the agreement will be new advanced photodefinable epoxy-based materials. They will be directed at wafer level packaging, 3D and through-silicon via (TSV) semiconductor packaging applications that are transforming electronics to make them smaller, lighter weight, more functional and more cost-effective.
“Combining the expertise of Nippon Kayaku and MicroChem in advanced epoxy resins and formulation, with DuPont coating technology, material science and electronic applications knowledge means that we can generate a series of enabling materials faster,” said Mats Ehlin, global business manager, DuPont Wafer Level Packaging Solutions. “We’re excited about this opportunity to further expand our offering and strengthen our ability to help customers meet their needs for improved performance, form factor and reduced cost.”
DuPont estimates the materials market for wafer level packaging, 3D and TSV will grow from about USD 100 million in 2009, to more than USD 600 million in 2013, and could as much as double to USD 1.2 billion by 2015. Wafer level packaging is spreading rapidly as a way to significantly improve the efficiency and reduce the size of semiconductor packages.