SEMATECH Presents Papers on New Materials for Emerging Semiconductor Technologies

SEMATECH engineers reported on materials and device structures that will define next generation CMOS and non-CMOS technologies at the 2010 Symposia on VLSI Technology and Circuits, June 15-18, at the Hilton Hawaiian Village in Honolulu, Hawaii.

Researchers at SEMATECH are focusing on techniques for simultaneously enhancing performance and reducing power consumption to enable the extension of CMOS logic and memory technologies. SEMATECH papers at VLSI, selected from hundreds of submissions, outlined new materials, processes and concepts, and described the way current semiconductor technologies can benefit from performance-enhancing features for future scaling needs.

“Identifying the optimum processes, materials, and device structures, and how they function when combined as a module, is of critical importance in pushing conventional CMOS scaling to its limits and paving the way for emerging beyond CMOS technologies,” said Raj Jammy, SEMATECH vice president of materials and emerging technologies. “The research that was presented at the VLSI symposium demonstrates SEMATECH’s leadership and innovative thinking as we help the industry develop future generations of low power, high performance IC devices that are both manufacturable and affordable.”

SEMATECH front-end process technologists reported the following technical advances:

• Investigating low contact resistance FinFETs with SOI substrates as a promising device structure for 22 nm and beyond: SEMATECH reported on a method to reduce parasitic resistance, a key issue affecting FinFET performance. While future narrow fin geometries reduce the area available for current flow through the silicon/silicide interface, reducing the interface barrier height in a simple and manufacturable way can realize significant performance improvements.
• Thoroughly exploring orientation and strain to enable a combination that simultaneously provides strong NMOS and PMOS: SEMATECH demonstrated a high mobility SiGe (110) channel CMOS with performance-boosting techniques. SEMATECH’s work advances high mobility channel CMOS technology with monolithic integration on a single SiGe (110)<110> channel orientation.
• Significant improvements in tunnel-FET transistors: In a project funded by DARPA and in collaboration with Prof. Chenming Hu of the University of California, Berkeley, SEMATECH researchers have enhanced this new class of devices aimed at lowering power dissipation in semiconductor devices. Tunneling transistors may be the answer to overcome the constraints posed by power dissipation in conventional CMOS scaling. SEMATECH reported an industry breakthrough—46mV/dec of sub-threshold swing—an important first step in realizing tunneling transistors.

In a short course series entitled, “Emerging Logic and Memory Technologies for VLSI Implementation,” Sitaram Arkalgud, director of SEMATECH’s 3D interconnect program, and Prashant Majhi, program manager of the CMOS scaling effort, presented on 3D interconnects and high mobility non-silicon channels. Specifically, Arkalgud discussed process development, module integration, and the overall manufacturability outlook for via-mid through-silicon vias (TSVs), a front-end process that allows the interconnect length to be shortened as well as the bandwidth between the stacked chips to be increased, resulting in lower power, higher performance, and increased device density. Dr. Majhi described the critical need for high mobility non-Si channels to enhance performance and reduce the power dissipation in future CMOS devices. Furthermore, he outlined breakthrough results from SEMATECH’s FEP research team, which is leading a multi-pronged effort to demonstrate the feasibility of integrating high mobility III-V channel materials on a silicon platform and developing the infrastructure needed by the industry to implement such devices at future nodes.

In conjunction with VLSI, SEMATECH and IMEC co-hosted an invitational workshop entitled “High Mobility Channels” on June 17. In a series of presentations and panel discussions, the workshop featured experts from industry and academia debating the challenges and opportunities—from device, process, tooling, and metrology perspectives—related to large-scale III-V manufacturing on silicon in a CMOS environment. Majhi shared highlights of SEMATECH’s efforts and its success in developing a fully functional test vehicle in a 200 mm flow. Several other industry experts and leading faculty researchers presented the results of their work. The panel of experts and audience concluded that III-V on Si is a next step in the evolution of Si CMOS and perhaps is necessary to keep power down in future generation chips.

The Symposium on VLSI Technology and Circuits is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities, and other research institutions that are key to SEMATECH’s ambitious research endeavors. It is sponsored by the IEEE Electron Devices Society and Solid-State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers.