May 14 2013
Cadence Design Systems today announced that it helped Yamaha Corporation reduce power consumption for its mobile consumer chips with characterization tools that delivered a 10 percent reduction in dynamic power to the clock network required for Yamaha ASICs.
In addition, the Cadence® characterization solution--composed of the Virtuoso® Liberate™ and Spectre® products--provided a 2x speedup in turnaround time for characterization when compared to Yamaha’s previous technology. The benefits translate to better power performance in chips that get to market faster.
“Cadence offered the only solution capable of characterizing our complex multi-bit cells,” said Mr. Shuhei Ito, development director, semiconductor division at Yamaha. “The Virtuoso Liberate and Spectre tools were critical in helping us develop our new low-power solution and in meeting our time to market goals.”
“Yamaha’s previous technology was unable to characterize the complex multi-bit flip-flop cells required for the low-power flow Yamaha adopted,” said Dr. Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. “With its patented “Inside View” technology, the Virtuoso Liberate tools enabled Yamaha to characterize these cells automatically by eliminating the need for the user to define the functional description of the cell or specify worst-case conditions. The Cadence characterization solution meets the ease-of-use, throughput and accuracy requirements that has helped Yamaha engineers reduce power for mobile applications while cutting characterization runtimes in half.”