Scalable 3D Chips with High-Speed Interconnections

Researchers at the Massachusetts Institute of Technology have developed a technique to create a multilayered chip with alternating layers of high-quality semiconducting material grown directly on top of one another. The findings were published in Nature.

The electronics industry is approaching the limits of integrating transistors onto a single chip surface. To address this, chip makers are exploring vertical stacking rather than further miniaturizing components. This approach involves layering multiple surfaces of transistors and semiconducting elements, similar to turning a single-story building into a high-rise. Such multilayered chips could process more complex tasks and handle significantly larger volumes of data than current designs.

One major challenge in stacking chips lies in the reliance on silicon wafers as the platform for constructing semiconductors. In traditional designs, each layer would require a thick silicon substrate, which would slow communication between the functional layers of the chip.

MIT engineers have addressed this challenge with a multilayered chip design that operates at low enough temperatures to preserve the underlying circuitry while eliminating the need for silicon wafer substrates. The novel technique enables the growth of high-performance semiconducting layers directly on top of one another.

Rather than depending on large silicon wafers, the method allows engineers to build transistors, memory, and logic components on a variety of crystalline surfaces. Removing the thick silicon substrates brings semiconducting layers closer to each other, improving interlayer communication and boosting computational performance.

The researchers suggest that this technique could lead to advanced AI hardware, such as stacked chips for laptops or wearables, with performance comparable to modern supercomputers and data storage capabilities similar to those in data centers.

This breakthrough opens up enormous potential for the semiconductor industry, allowing chips to be stacked without traditional limitations. This could lead to orders-of-magnitude improvements in computing power for applications in AI, logic, and memory.

Jeehwan Kim, Study Author and Associate Professor, Department of Mechanical Engineering, Massachusetts Institute of Technology

The study’s MIT co-authors include first author Ki Seok Kim, Seunghwan Seo, Doyoon Lee, Jung-El Ryu, Jekyung Kim, Jun Min Suh, June-chul Shin, Min-Kyu Song, Jin Feng, and Sangho Lee, along with collaborators from Samsung Advanced Institute of Technology, Sungkyunkwan University in South Korea, and the University of Texas at Dallas.

Seed Pockets

In 2023, Kim's team reported a technique for growing high-quality semiconducting materials on amorphous surfaces, mimicking the complex topography of semiconducting circuitry on finished chips. They focused on cultivating a class of two-dimensional materials known as transition-metal dichalcogenides (TMDs), which are considered a promising alternative to silicon for producing high-performance, smaller transistors. Unlike silicon, which loses performance at atomic scales, these 2D materials retain their semiconducting properties even at extremely small dimensions.

Previously, the team grew TMDs on existing TMD layers and on silicon wafers with amorphous coatings. To achieve this, they used a thin silicon dioxide "mask" patterned with tiny holes or pockets. This mask was applied over a silicon wafer to guide the arrangement of atoms into high-quality, single-crystalline structures rather than disordered polycrystalline forms. When exposed to an atom gas, the atoms settled into the pockets, acting as "seeds" that grew into ordered, single-crystalline patterns.

However, at the time, the technique only worked at temperatures of around 900 ℃.

You have to grow this single-crystalline material below 400 ℃, otherwise the underlying circuitry is completely cooked and ruined. So, our homework was, we had to do a similar technique at temperatures lower than 400 ℃. If we could do that, the impact would be substantial.

Jeehwan Kim, Study First Author and Associate Professor, Department of Mechanical Engineering, Massachusetts Institute of Technology

Building Up

Kim and colleagues aimed to refine their process to grow single-crystalline 2D materials at temperatures low enough to preserve existing circuitry. They found inspiration in metallurgy, where molten metal forms grains, or "nucleates," at the edges of a mold. These grains grow and combine into regularly patterned crystals as the metal solidifies. Metallurgists have observed that nucleation occurs more easily and with less energy at the mold’s edges.

Kim said, “It’s known that nucleating at the edges requires less energy — and heat. So we borrowed this concept from metallurgy to utilize for future AI hardware.”

The team’s goal was to grow single-crystalline TMDs directly on a silicon wafer already fabricated with transistor circuitry. Using a silicon dioxide mask similar to their earlier work, they found that TMD seeds deposited at the edges of each pocket grew into single-crystalline material at temperatures as low as 380 ℃. By contrast, seeds deposited in the center required higher temperatures to form single crystals.

To advance their work, the researchers developed a method to create a multilayered chip with alternating layers of two distinct TMDs: tungsten diselenide, suitable for p-type transistors, and molybdenum disulfide, a candidate for n-type transistors. P- and n-type transistors are essential building blocks for logic operations.

Without intermediate silicon wafers, the team successfully grew both materials in single-crystalline form directly on top of one another. According to Kim, this technique could double the density of a chip’s semiconducting components, particularly complementary metal-oxide semiconductors (CMOS), which are integral to modern logic circuits.

Kim continued, “A product realized by our technique is not only a 3D logic chip but also 3D memory and their combinations. With our growth-based monolithic 3D method, you could grow tens to hundreds of logic and memory layers, right on top of each other, and they would be able to communicate very well.”

He added, “Conventional 3D chips have been fabricated with silicon wafers in-between, by drilling holes through the wafer — a process which limits the number of stacked layers, vertical alignment resolution, and yields. Our growth-based method addresses all of those issues at once.”

To advance the commercialization of their stackable chip design, Kim founded FS2 (Future Semiconductor 2D materials).

Kim concluded, “We so far show a concept at a small-scale device arrays. The next step is scaling up to show professional AI chip operation.”

The study received partial funding from the US Air Force Office of Scientific Research and the Samsung Advanced Institute of Technology.

A Guide to Semiconductor Chip Layers

Journal Reference:

Kim, S, K., et al. (2024) Growth-based monolithic 3D integration of single-crystal 2D semiconductors. Nature. doi.org/10.1038/s41586-024-08236-9