Dec 7 2004
Marking the latest milestone in their joint effort to commercialize strained silicon-on-insulator (sSOI) technology, the Soitec Group and ASM International N.V. today announced they have produced samples of the industry’s first industrially manufactured 300-mm sSOI wafers. This milestone was driven by positive results from customer evaluation of 200-mm sSOI sample wafers, which was announced last year. The first 300-mm sSOI wafer from these newly engineered substrates will be showcased in the Soitec Asia booth located at #7A-1001 at this year’s SEMICON Japan show being held December 1-3, 2004 at the Makuhari Messe. Soitec and ASM also announced that they have decided to extend their partnership to further improve manufacturing efficiency and develop next-generation sSOI products.
Soitec and ASM report that the quality of the 300-mm sSOI wafers corresponds very closely to that achieved at 200-mm, underscoring the scalability of Soitec’s Smart Cut™ process for the transition to production-scale manufacturing of these larger-diameter wafers. The sSOI wafers exhibit a strain value of 1.5 Giga Pascal (GPa) with homogeneity of ±7 percent over the wafer. The recorded strain corresponds to a silicon lattice deformation of almost 1 percent. The strained silicon layer thickness is 200 Å with homogeneity of ±3 percent and a surface roughness comparable to that of premium bulk silicon wafers. Internal testing has shown that the Soitec sSOI wafers maintain their strain at temperatures up to 1100°C, offering a process window sufficient to accommodate CMOS integration thermal budgets.
“The successful production of 300-mm sSOI wafer samples takes this project beyond R&D evaluation and into the next phase of industrialization, enabling Soitec to make these wafers available for developing ICs at the 45-nm technology node,” said Carlos Mazuré, Soitec’s chief technology officer. “This latest milestone emphasizes our ability to focus on developing, in an extremely short period of time, engineered substrates that meet the stringent requirements of future technology nodes in 300 mm.”
A key contribution to the industrial development of 300-mm sSOI wafers based on Smart Cut technology was the introduction of the Epsilon® 3200 epitaxial production reactor earlier this year. This throughput-enhanced model was installed in Soitec’s Bernin production line at the beginning of 2004, and is based on ASM’s production line proven E3000 300-mm silicon epitaxial reactor. According to Armand Ferro, Business Unit Manager for epitaxy at ASM America, Phoenix, “Several enhancements introduced in the E3200 also enable the growth of lattice-relaxed silicon germanium layers and strained silicon layers with unparalleled thickness and composition control, as well as a unique combination of a high strain level and low defect density.”
These 300-mm sSOI engineered substrates are the result of a focused two-year development program between Soitec and ASM. Initiated in February 2003, the partnership has steadily yielded success with the two companies striving to bring sSOI substrates to commercial fruition. A strong advantage of sSOI substrates is that the mobility enhancement factor is built into the substrate, thus spreading the “strain” benefits to all regions of the IC and to all transistor geometries. Moreover, with wafer-level strain no longer dependent on IC design, sSOI substrates will enable a wider range of high-speed, low-power IC applications, including those with high-performance logic cores. This will allow chipmakers to access sSOI substrates that promise to break through power-dissipation barriers—an increasingly critical roadblock to higher-performing chips, particularly as the industry moves toward sub-65-nm IC development.
The initial 300-mm wafers are thin-film sSOI for fully depleted (FD) architectures; thicker-film sSOI wafers for partially depleted (PD) architectures will begin sampling during the first quarter of 2005.
For more information on integrated circuits, click here.