May 23 2014
Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced a new integrated solution to significantly cut down die-package interconnect planning time from weeks to days by reducing iterations between silicon and package design teams.
The solution, built on Cadence® OrbitIO™ technology, also shortens the time to converge on the physical interface between the die and package up to 60 percent, all within the context of the full system.
Building on its leadership position for co-design in the implementation stage, Cadence OrbitIO technology is used earlier in the design cycle to provide rapid interconnect planning of high-performance interfaces across multiple fabrics. As part of an overall co-design solution, Cadence OrbitIO technology provides seamless integration with Cadence SiP Layout and the Cadence Encounter® digital implementation platform. This integrated solution allows design teams to clearly communicate design intent throughout the flow, resulting in better decision-making, fewer iterations and shorter cycle-times. It can enable fabless semiconductor or systems companies to evaluate package route feasibility, and allows them to communicate a route plan to their package design resources, whether it is to an internal group or to an outsourced assembly and test (OSAT) provider.
"The Cadence OrbitIO global view of system connectivity helps Faraday reduce the time required to converge on the optimal die bump to package ball pad assignment," said Dr. Wang-Jin Chen, senior technologist of Faraday. "The combination of connectivity optimization and route feasibility functions helped us produce a route plan resulting in two fewer package layers with all DDR signals implemented on a single package layer."
To learn more about OrbitIO technology, please visit: www.cadence.com/products/sigrity/orbitio/pages/default.aspx